Recently, the requirements for downsizing and weight reduction, and a high-function and high-performance of electronic equipment have been getting more and more intense, and the amount of handled data has been increasing dramatically.
With this, the memory capacity of a semiconductor memory that is mounted on the electronic equipment also increases, and a semiconductor memory that has a high data transfer rate is required.
Generally, as semiconductor devices that are loaded on electronic equipment of this kind, there are a System-on-Chip (SoC) such that the logic (controller) and the memory are integrated into one chip, and a System-in-Package (SiP) such that the logic chip and the memory chip are laminated and stored in one package.
For the SoC, the semiconductor processes are complicated, and the costs become high in accordance with that. In contrast to this, since the SiP is constituted by packaging plural semiconductor chips that have been individually manufactured utilizing existing semiconductor processes, it is not necessary to develop new semiconductor processes, and the manufacturing costs are comparatively low. Because of this, electronic equipment with the SiP utilized tends to increase nowadays.
Moreover, for the SiP, in order that the parasitic LCR is allowed to be small and the data transfer rate is allowed to be high, a Chip-on-Chip (CoC) technology has been developed such that direct flip chip connections are carried out between the chips via micro bumps and the like.
In a semiconductor device with such a CoC technology utilized, generally, the logic chip is arranged on the lower side and the memory chip is laminated on the upper side but, when the memory capacity of the memory chip becomes large, it tends to get larger in size than the logic chip. Accordingly, in such a case it is general that the memory chip is arranged on the lower side and the logic chip is laminated on the upper side (for example, see Japanese published patent application 2008-10759).
In this case, also in a semiconductor device with the CoC technology as described above utilized, since external connection terminals (pads) have been provided separately with respect to the logic chip and the memory chip, it has been necessary to specially ensure regions for forming the external connection terminals in respective chips. Besides, it is necessary to form a through electrode (TSV) in either of the logic chip and the memory chip, and cost lowering by downsizing of each chip itself and manufacturing process reducing has been unable to be sufficiently accomplished.
In order to solve this problem, there is also such a one for which downsizing as the whole of a semiconductor device and reducing of the manufacturing process have been achieved with the terminals for external connection collected on the semiconductor memory chip side, by the above-described CoC technology, in a semiconductor device configured so that the semiconductor logical circuit chip that is smaller in size than the semiconductor memory chip is laminated (for example, see Japanese published patent application 2010-141080).
In FIG. 10(a), is shown a sectional view that shows the constitution of an electronic component implementing structure body that is disclosed in Japanese published patent application 2010-141080.
In one face of the semiconductor memory chip 81, the terminal 83 for external connection is formed in the connection terminal 86 and the outer fringe part, and the connection terminal 86 and the terminal 83 for external connection are electrically connected via the internal wiring layer of the semiconductor memory chip 81. On the connection terminal 86, the protruding electrode 87 is formed.
The semiconductor logical circuit chip 80 with the connection terminal 85 formed in one face is, by the CoC, laminated to the semiconductor memory chip 81 so that the connection terminal 85 electrically comes in contact with the protruding electrode 87.
Moreover, the semiconductor memory chip 81 is laminated on the interposer substrate 82, and the connection terminal 84 formed in one face of the interposer substrate 82 is connected via the through hole 88 to the protruding electrode 89 that is formed in the opposite face.
By connecting, by wire bonding and the like with the wire 91, the terminal 83 for external connection of the semiconductor memory chip 81 and the connection terminal 84 of the interposer substrate 82, the connection terminal 85 of the semiconductor logical circuit chip 80 is electrically connected, via the protruding electrode 87, the connection terminal 86, the terminal 83 for external connection, the wire 91, the connection terminal 84 and the through hole 88, to the protruding electrode 89 of the opposite face of the interposer substrate 82.
By making constitution like this, establishment of external connection terminals in the semiconductor logical circuit chip 80 is allowed to be unnecessary, and downsizing of the whole of the semiconductor device is realized.